Home › Core › ISCC-IDs › 28CrZhsLTth1H

View ISCC-ID

Core Data

28CrZhsLTth1H
ISCC-ID - digital asset identifier
CCLV6rHDeKqJg-CT2dRPKGX8cVx-CDhf4xbrTqGnT-CRGnuLzUDNGxJ
ISCC-CODE - digital asset descriptor
2QTa5N4aeSrCB2MLoPdPF4AsTjstJgcLTnd
PUBLIC-KEY or WALLET-ADDRESS of DECLARING PARTY
0
Number of times updated

Seed Metadata (Immutable)

design and realization of a 24 gbps 32 gbps clock and data recovery circuit using deepsubmicron digital cmos technology

Ledger Reference

coblo
Source Ledger/Blockchain
668112
N-th ISCC Decleration on source ledger
0eae49bd5d10f30b18b60a045eeff7c985fd695fa6feff68fc414ecb303007c0
Hash of block that includes the ISCC-DECLARATION
3f6d27d8c9e9a6c1c62172b0766d7de1335800e2ee67fff8b0dd156f538392aa
Hash of transaction that includes the ISCC-DECLERATION
0
Output index that includes ISCC-DECLERATION (UTXO based chains)

Mutable Metadata

[{"data": {"name": "Design and realization of a 2.4 Gbps - 3.2 Gbps clock and data recovery circuit using deep-submicron digital CMOS technology", "@type": "ScholarlyArticle", "genre": "proceedings-article", "author": [{"name": "Z.O. Gursoy", "@type": "Person"}, {"name": "Y. Leblebici", "@type": "Person"}], "@context": "http://schema.org/", "encoding": [{"@type": "MediaObject", "contentUrl": "http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.169.6878&rep=rep1&type=pdf", "encodingFormat": "application/pdf"}], "publisher": {"name": "IEEE", "@type": "Organization"}, "identifier": [{"@type": "PropertyValue", "value": "10.1109/soc.2003.1241471", "propertyID": "DOI"}, {"@type": "PropertyValue", "value": "CCLV6rHDeKqJg-CT2dRPKGX8cVx-CDhf4xbrTqGnT-CRGnuLzUDNGxJ", "propertyID": "ISCC"}]}, "schema": "schema.org", "mediatype": "application/ld+json"}]
Close