[{"data": {"name": "Planarization Polishing Technique for Large Diameter of Bare Silicon Wafer", "@type": "ScholarlyArticle", "genre": "journal-article", "author": [{"name": "Hatsuyuki ARAI", "@type": "Person"}], "@context": "http://schema.org/", "encoding": [{"@type": "MediaObject", "contentUrl": "https://www.jstage.jst.go.jp/article/jjspe/73/7/73_7_756/_pdf", "encodingFormat": "application/pdf"}], "publisher": {"name": "Japan Society for Precision Engineering", "@type": "Organization"}, "identifier": [{"@type": "PropertyValue", "value": "10.2493/jjspe.73.756", "propertyID": "DOI"}, {"@type": "PropertyValue", "value": "CCiwEndBZWGBp-CTKag5ByXh9qK-CDDHRR22S28q8-CRFEtq2qibctV", "propertyID": "ISCC"}], "datePublished": "2007-01-01"}, "schema": "schema.org", "mediatype": "application/ld+json"}]